As fabrication methods have improved and smaller geometry technologies, such as 90-nanometer design, have been developed, the area of silicon required to produce a memory device having a given data storage capacity has continued to decrease. Generally, these technological advances have led to a greater number of memory devices per silicon wafer, and consequently, a lower cost per memory device. Meanwhile, the overall storage capacity of memory devices has been continuously increasing. Unfortunately, this trend has resulted in significantly increasing the complexity involved in the testing of some memory devices. In particular, it has become increasingly challenging to rapidly and cost-effectively identify manufacturing defects in volatile memory devices, such as CMOS SRAM memory devices.
An SRAM memory cell is a volatile memory cell that uses a flip-flop circuit to store data. In contrast, a dynamic random access memory (DRAM) cell utilizes a single transistor in conjunction with a capacitor that requires continuous refreshing to retain its data. Defects in both types of volatile memory lead to potential stability or data retention problems.
FIG. 1 illustrates a schematic diagram of an example prior art six-transistor memory cell 10 commonly used in CMOS SRAM memory devices. As illustrated in FIG. 1, the SRAM memory cell 10 includes two N-channel field effect transistors (FETs) (e.g., T1 and T2) interconnected with two cross-coupled P-channel transistors (e.g., T3 and T4). A second pair of N-channel transistors (e.g., T5 and T6) have their gate terminals connected to the word-line and serve as “pass” gates to close the paths between the bit-lines BIT and #BIT# (where #BIT# indicates that an opposite, or complementary, logic state is asserted on the bit-line when setting the memory cell 10 to a particular logic state) and the memory transistors T1 and T2 of the cell.
In the SRAM memory cell 10 illustrated in FIG. 1, if the pull-up P-devices (e.g., transistors T3 and T4) are too weak due to a fabrication defect, the memory cell 10 may be able to write and store the input data, but may nonetheless fail to retain the logic value over time. The resulting fault in a defective cell is generally referred to as a data retention fault. In a defective memory cell, the retention time generally depends on the nature of the defect including the level of current leakage as well as the node capacitance. For example, if current leakage is high and/or the node capacitance is low, the memory cell may undesirably “flip” its logical state after a period of time.
Traditionally, data retention faults have been tested by writing a logical “0” or logical “1” to a memory cell, waiting an appropriate amount of time, and then reading back the value to verify that it is the same value that was originally written. However, given the number of memory cells involved and the amount of wait time required to detect a data retention fault, such testing is extremely time consuming and significantly adds to manufacturing costs.
To further complicate matters, it is increasingly common for memory devices to be embedded in computer chips, for example, application specific integrated circuits (ASICs) and/or systems-on-a-chip (SoCs). When a memory device is embedded, it may become more difficult to access the bit-lines and word-lines of the memory device, thereby making it even more difficult to test the memory device.